diff options
| author | Kuppuswamy Sathyanarayanan | 2017-04-09 15:00:16 -0700 |
|---|---|---|
| committer | Andy Shevchenko | 2017-04-28 21:51:26 +0300 |
| commit | e6749c89b4b0acaeddf4909eb75b7f6c8a4c15b2 (patch) | |
| tree | a71769c515be7bf45c68d02650202bc49c98b3a7 /arch/x86/include | |
| parent | 9216e0dcb5533a999d544d0af8661118e0588e1d (diff) | |
platform/x86: intel_pmc_ipc: fix gcr offset
According to Broxton APL spec, PMC MIMO resources for Global Control
Registers(GCR) are located at 4K(0x1000) offset from IPC base address.
In this driver, PLAT_RESOURCE_GCR_OFFSET macro defines the offset of GCR
region base address from IPC base address and its current value of
0x1008 is incorrect because it points to location for PMC_CFG register
and not the GCR base address itself.
GCR Base = IPC1 Base + 0x1000.
This patch fixes this offset issue.
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Diffstat (limited to 'arch/x86/include')
0 files changed, 0 insertions, 0 deletions