diff options
| author | Scott Telford | 2016-09-15 16:26:45 +0100 |
|---|---|---|
| committer | Max Filippov | 2016-09-19 11:51:32 -0700 |
| commit | bebbc4bcf36f015a5a051cc8817b11de209fbe8b (patch) | |
| tree | e0dd6dbdafc17293c491524ce1786a4df5ddc4da /arch/xtensa/boot | |
| parent | bf15f86b343ed894e74fb9c6c944cea1f8f9b654 (diff) | |
xtensa: Tweak xuartps UART driver Rx watermark for Cadence CSP config.
Add module parameter xilinx_uartps.rx_trigger_level=32 to command line
options for CSP to set Rx watermark for xuartps driver lower than the
default value, to avoid UART overruns at 115200 bps.
Signed-off-by: Scott Telford <stelford@cadence.com>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'arch/xtensa/boot')
| -rw-r--r-- | arch/xtensa/boot/dts/csp.dts | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/xtensa/boot/dts/csp.dts b/arch/xtensa/boot/dts/csp.dts index 197aeadb3f90..4082f26716b9 100644 --- a/arch/xtensa/boot/dts/csp.dts +++ b/arch/xtensa/boot/dts/csp.dts @@ -7,7 +7,7 @@ interrupt-parent = <&pic>; chosen { - bootargs = "earlycon=cdns,0xfd000000,115200 console=tty0 console=ttyPS0,115200 root=/dev/ram0 rw earlyprintk loglevel=8 nohz=off ignore_loglevel"; + bootargs = "earlycon=cdns,0xfd000000,115200 console=tty0 console=ttyPS0,115200 root=/dev/ram0 rw earlyprintk xilinx_uartps.rx_trigger_level=32 loglevel=8 nohz=off ignore_loglevel"; }; memory@0 { |