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authorNishanth Menon2015-09-03 14:23:45 -0500
committerTony Lindgren2015-09-16 17:00:29 -0700
commit5005296e7408c055a02fc8be9f62218cb4b52b13 (patch)
tree9e09b8a01417c15c40646018095ebd6f327d0abb /arch/xtensa
parent7168e947291f0ead07e5638b4599fb7845288b69 (diff)
ARM: dts: am57xx-beagle-x15: Update Phy supplies
Originally, all the SoC PHY rails were supplied by LDO3. However, as a result of characterization, it was determined that this posed a risk in extreme load conditions. Hence the PHY rails are split between two different LDOs. Update the related node as a result LDO3/VDDA_1V8_PHYA supplies vdda_usb1, vdda_usb2, vdda_sata, vdda_usb3 LDO4/VDDA_1V8_PHYB supplies vdda_pcie1, vdda_pcie0, vdda_hdmi, vdda_pcie NOTE: We break compatibility with pre-production boards with this change since, the PMIC LDO4 is disabled at OTP level. The new configuration is the plan of record and all pre-production boards are supposed to be replaced with the latest boards matching the mentioned configuration. Some very few 10 something boards have been created and stopped production till the latest modifications were done (PMIC USB interrupt, LDO4 etc) - and all of those boards are now getting scrapped.. If there are any (as per tracking information, there should not be any), TI should be contacted to have them replaced. Signed-off-by: Nishanth Menon <nm@ti.com> [tony@atomide.com: updated commit about these being TI internal protos] Signed-off-by: Tony Lindgren <tony@atomide.com>
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