diff options
| author | Masahiro Yamada | 2017-02-27 14:28:41 -0800 |
|---|---|---|
| committer | Linus Torvalds | 2017-02-27 18:43:46 -0800 |
| commit | 08a7e621ff81dec64ddf1eab16353c0c217fdd89 (patch) | |
| tree | 2a256441b8c5b377d190edd12419ae9323fa570e /arch | |
| parent | f3048d17d1127f003db10fb8ac9a68610923f783 (diff) | |
scripts/spelling.txt: add "swith" pattern and fix typo instances
Fix typos and add the following to the scripts/spelling.txt:
swith||switch
swithable||switchable
swithed||switched
swithing||switching
While we are here, fix the "update" to "updates" in the touched hunk in
drivers/net/wireless/marvell/mwifiex/wmm.c.
Link: http://lkml.kernel.org/r/1481573103-11329-2-git-send-email-yamada.masahiro@socionext.com
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/compressed/head.S | 2 | ||||
| -rw-r--r-- | arch/arm/mm/cache-v7.S | 2 | ||||
| -rw-r--r-- | arch/arm/mm/cache-v7m.S | 2 | ||||
| -rw-r--r-- | arch/sh/kernel/irq.c | 2 | ||||
| -rw-r--r-- | arch/sparc/include/asm/switch_to_32.h | 2 |
5 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index fc6d541549a2..9150f9732785 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -1196,7 +1196,7 @@ skip: bgt loop1 finished: ldmfd sp!, {r0-r7, r9-r11} - mov r10, #0 @ swith back to cache level 0 + mov r10, #0 @ switch back to cache level 0 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr iflush: mcr p15, 0, r10, c7, c10, 4 @ DSB diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index a134d8a13d00..de78109d002d 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -164,7 +164,7 @@ skip: cmp r3, r10 bgt flush_levels finished: - mov r10, #0 @ swith back to cache level 0 + mov r10, #0 @ switch back to cache level 0 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr dsb st isb diff --git a/arch/arm/mm/cache-v7m.S b/arch/arm/mm/cache-v7m.S index 816a7e44e6f1..788486e830d3 100644 --- a/arch/arm/mm/cache-v7m.S +++ b/arch/arm/mm/cache-v7m.S @@ -217,7 +217,7 @@ skip: cmp r3, r10 bgt flush_levels finished: - mov r10, #0 @ swith back to cache level 0 + mov r10, #0 @ switch back to cache level 0 write_csselr r10, r3 @ select current cache level in cssr dsb st isb diff --git a/arch/sh/kernel/irq.c b/arch/sh/kernel/irq.c index bc3591125df7..04487e8fc9b1 100644 --- a/arch/sh/kernel/irq.c +++ b/arch/sh/kernel/irq.c @@ -99,7 +99,7 @@ static inline void handle_one_irq(unsigned int irq) "mov %0, r4 \n" "mov r15, r8 \n" "jsr @%1 \n" - /* swith to the irq stack */ + /* switch to the irq stack */ " mov %2, r15 \n" /* restore the stack (ring zero) */ "mov r8, r15 \n" diff --git a/arch/sparc/include/asm/switch_to_32.h b/arch/sparc/include/asm/switch_to_32.h index 16f10374feb3..475dd4158ae4 100644 --- a/arch/sparc/include/asm/switch_to_32.h +++ b/arch/sparc/include/asm/switch_to_32.h @@ -9,7 +9,7 @@ extern struct thread_info *current_set[NR_CPUS]; * Flush windows so that the VM switch which follows * would not pull the stack from under us. * - * SWITCH_ENTER and SWITH_DO_LAZY_FPU do not work yet (e.g. SMP does not work) + * SWITCH_ENTER and SWITCH_DO_LAZY_FPU do not work yet (e.g. SMP does not work) * XXX WTF is the above comment? Found in late teen 2.4.x. */ #ifdef CONFIG_SMP |