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| author | Rahul Tanwar | 2022-10-13 14:48:33 +0800 |
|---|---|---|
| committer | Greg Kroah-Hartman | 2023-02-25 11:25:38 +0100 |
| commit | 3391bea3d6b81822f1d61f1c62103719303396f0 (patch) | |
| tree | 97c40c54fdd8651d300c235988f5cdf4ce074c5f /arch | |
| parent | 77fee59653c63d3b771a28a4a0f76b80b330aa9a (diff) | |
clk: mxl: Fix a clk entry by adding relevant flags
[ Upstream commit 106ef3bda21006fe37b62c85931230a6355d78d3 ]
One of the clock entry "dcl" clk has some HW limitations. One is that
its rate can only by changed by changing its parent clk's rate & two is
that HW does not support enable/disable for this clk.
Handle above two limitations by adding relevant flags. Add standard flag
CLK_SET_RATE_PARENT to handle rate change and add driver internal flag
DIV_CLK_NO_MASK to handle enable/disable.
Fixes: d058fd9e8984 ("clk: intel: Add CGU clock driver for a new SoC")
Reviewed-by: Yi xin Zhu <yzhu@maxlinear.com>
Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>
Link: https://lore.kernel.org/r/a4770e7225f8a0c03c8ab2ba80434a4e8e9afb17.1665642720.git.rtanwar@maxlinear.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'arch')
0 files changed, 0 insertions, 0 deletions