diff options
| author | Maciej W. Rozycki | 2005-06-14 17:35:03 +0000 |
|---|---|---|
| committer | Ralf Baechle | 2005-10-29 19:31:22 +0100 |
| commit | aac8aa7717a23a9bf8740dbfb59755b1d62f04bf (patch) | |
| tree | cae373db64607dafc496827c0d2f3b67b91d880f /arch | |
| parent | fded2e508a1d3c26ab477ab3b98f13274d4359ba (diff) | |
Enable a suitable ISA for the assembler around ll/sc so that code
builds even for processors that don't support the instructions.
Plus minor formatting fixes.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/kernel/semaphore.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/arch/mips/kernel/semaphore.c b/arch/mips/kernel/semaphore.c index 9c40fe5a8e8d..dbb145ee00a7 100644 --- a/arch/mips/kernel/semaphore.c +++ b/arch/mips/kernel/semaphore.c @@ -42,24 +42,28 @@ static inline int __sem_update_count(struct semaphore *sem, int incr) if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( - "1: ll %0, %2 \n" + " .set mips2 \n" + "1: ll %0, %2 # __sem_update_count \n" " sra %1, %0, 31 \n" " not %1 \n" " and %1, %0, %1 \n" - " add %1, %1, %3 \n" + " addu %1, %1, %3 \n" " sc %1, %2 \n" " beqzl %1, 1b \n" + " .set mips0 \n" : "=&r" (old_count), "=&r" (tmp), "=m" (sem->count) : "r" (incr), "m" (sem->count)); } else if (cpu_has_llsc) { __asm__ __volatile__( - "1: ll %0, %2 \n" + " .set mips2 \n" + "1: ll %0, %2 # __sem_update_count \n" " sra %1, %0, 31 \n" " not %1 \n" " and %1, %0, %1 \n" - " add %1, %1, %3 \n" + " addu %1, %1, %3 \n" " sc %1, %2 \n" " beqz %1, 1b \n" + " .set mips0 \n" : "=&r" (old_count), "=&r" (tmp), "=m" (sem->count) : "r" (incr), "m" (sem->count)); } else { |