diff options
| author | Ralf Baechle | 2005-12-08 13:00:20 +0000 |
|---|---|---|
| committer | 2006-01-10 13:39:06 +0000 | |
| commit | e7958bb90d57f0da073cbd031a1808de51d1de15 (patch) | |
| tree | b4f0d57ab157c64ce23722dbd29864901794a019 /arch | |
| parent | 571e0bed85470882cedfb100e847902911c3f4d2 (diff) | |
MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/kernel/cpu-probe.c | 12 | ||||
| -rw-r--r-- | arch/mips/kernel/time.c | 2 | ||||
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 4 |
3 files changed, 9 insertions, 9 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 5e1b08b00a33..d00f8768e2a0 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -447,10 +447,10 @@ static inline unsigned int decode_config0(struct cpuinfo_mips *c) isa = (config0 & MIPS_CONF_AT) >> 13; switch (isa) { case 0: - c->isa_level = MIPS_CPU_ISA_M32; + c->isa_level = MIPS_CPU_ISA_M32R1; break; case 2: - c->isa_level = MIPS_CPU_ISA_M64; + c->isa_level = MIPS_CPU_ISA_M64R1; break; default: panic("Unsupported ISA type, cp0.config0.at: %d.", isa); @@ -568,7 +568,7 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c) break; case PRID_IMP_34K: c->cputype = CPU_34K; - c->isa_level = MIPS_CPU_ISA_M32; + c->isa_level = MIPS_CPU_ISA_M32R1; break; } } @@ -647,7 +647,7 @@ static inline void cpu_probe_philips(struct cpuinfo_mips *c) switch (c->processor_id & 0xff00) { case PRID_IMP_PR4450: c->cputype = CPU_PR4450; - c->isa_level = MIPS_CPU_ISA_M32; + c->isa_level = MIPS_CPU_ISA_M32R1; break; default: panic("Unknown Philips Core!"); /* REVISIT: die? */ @@ -690,8 +690,8 @@ __init void cpu_probe(void) if (c->options & MIPS_CPU_FPU) { c->fpu_id = cpu_get_fpu_id(); - if (c->isa_level == MIPS_CPU_ISA_M32 || - c->isa_level == MIPS_CPU_ISA_M64) { + if (c->isa_level == MIPS_CPU_ISA_M32R1 || + c->isa_level == MIPS_CPU_ISA_M64R1) { if (c->fpu_id & MIPS_FPIR_3D) c->ases |= MIPS_ASE_MIPS3D; } diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index 787ed541d442..174959bf1d59 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -628,7 +628,7 @@ void __init time_init(void) mips_hpt_init = c0_hpt_init; } - if ((current_cpu_data.isa_level == MIPS_CPU_ISA_M32) || + if ((current_cpu_data.isa_level == MIPS_CPU_ISA_M32R1) || (current_cpu_data.isa_level == MIPS_CPU_ISA_I) || (current_cpu_data.isa_level == MIPS_CPU_ISA_II)) /* diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 38223b44d962..422b55fab07a 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1183,8 +1183,8 @@ static void __init setup_scache(void) if (!sc_present) return; - if ((c->isa_level == MIPS_CPU_ISA_M32 || - c->isa_level == MIPS_CPU_ISA_M64) && + if ((c->isa_level == MIPS_CPU_ISA_M32R1 || + c->isa_level == MIPS_CPU_ISA_M64R1) && !(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); |