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| author | Dmitry Baryshkov | 2022-09-27 12:22:04 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman | 2022-12-31 13:32:48 +0100 |
| commit | 5d39a1d9a2435eae9e8e329cba07499041f20256 (patch) | |
| tree | 94f5068506722574e059745044fec9e0e3590a97 /certs | |
| parent | e83821af647144cc87afae1b65047d08aaf502ad (diff) | |
phy: qcom-qmp-pcie: Support SM8450 PCIe1 PHY in EP mode
[ Upstream commit f5682f13b7ab0bbdffd11934afe4b5c011d5be74 ]
Add support for using PCIe1 (gen4x2) in EP mode on SM8450. The tables to
program are mostly common with the RC mode tables, so only register
difference are split into separate RC and EP tables.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220927092207.161501-4-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Stable-dep-of: 9ddcd920f8ed ("phy: qcom-qmp-pcie: Fix high latency with 4x2 PHY when ASPM is enabled")
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'certs')
0 files changed, 0 insertions, 0 deletions