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| author | Manivannan Sadhasivam | 2022-11-02 13:48:34 +0530 |
|---|---|---|
| committer | Greg Kroah-Hartman | 2022-12-31 13:32:48 +0100 |
| commit | c5ca087f47def5645be252830585b1d69d83ca23 (patch) | |
| tree | 56d7821959874a108d8782320de7281bf366314f /certs | |
| parent | 5d39a1d9a2435eae9e8e329cba07499041f20256 (diff) | |
phy: qcom-qmp-pcie: Fix high latency with 4x2 PHY when ASPM is enabled
[ Upstream commit 9ddcd920f8edfe65c3670fbd0b49db00e1e562fe ]
The PCIe QMP 4x2 RC PHY generates high latency when ASPM is enabled. This
seem to be fixed by clearing the QPHY_V5_20_PCS_PCIE_PRESET_P10_POST
register of the pcs_misc register space.
Fixes: 2c91bf6bf290 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20221102081835.41892-1-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'certs')
0 files changed, 0 insertions, 0 deletions