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authorThor Thayer2015-06-04 09:28:46 -0500
committerBorislav Petkov2015-06-24 18:16:08 +0200
commit143f4a5ac5af82a4055100c8f40b26187d5c20ba (patch)
treeac65223b91db64f2823deefd7552f23e1d9ba116 /crypto/lrw.c
parentf9ae487e04370e229a96c83a8c86510299712192 (diff)
EDAC, altera: Refactor for Altera CycloneV SoC
The Arria10 SoC uses a completely different SDRAM controller from the earlier CycloneV and ArriaV SoCs. This patch abstracts the SDRAM bits for the CycloneV/ArriaV SoCs in preparation for the Arria10 support. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: devicetree@vger.kernel.org Cc: dinguyen@opensource.altera.com Cc: galak@codeaurora.org Cc: grant.likely@linaro.org Cc: ijc+devicetree@hellion.org.uk Cc: linux-arm-kernel@lists.infradead.org Cc: linux-edac <linux-edac@vger.kernel.org> Cc: m.chehab@samsung.com Cc: mark.rutland@arm.com Cc: pawel.moll@arm.com Cc: robh+dt@kernel.org Cc: tthayer.linux@gmail.com Link: http://lkml.kernel.org/r/1433428128-7292-3-git-send-email-tthayer@opensource.altera.com Signed-off-by: Borislav Petkov <bp@suse.de>
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