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author | Anup Patel | 2022-04-09 09:15:44 +0530 |
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committer | Anup Patel | 2022-04-09 09:15:44 +0530 |
commit | fac3725364397f9a40a101f089b86ea655a58d06 (patch) | |
tree | 19c4c4c501e86957c4f8c3b4d212d58120f8351a /crypto/pcbc.c | |
parent | 8c3ce496bd612bd21679e445f75fcabb6be997b2 (diff) |
KVM: selftests: riscv: Set PTE A and D bits in VS-stage page table
Supporting hardware updates of PTE A and D bits is optional for any
RISC-V implementation so current software strategy is to always set
these bits in both G-stage (hypervisor) and VS-stage (guest kernel).
If PTE A and D bits are not set by software (hypervisor or guest)
then RISC-V implementations not supporting hardware updates of these
bits will cause traps even for perfectly valid PTEs.
Based on above explanation, the VS-stage page table created by various
KVM selftest applications is not correct because PTE A and D bits are
not set. This patch fixes VS-stage page table programming of PTE A and
D bits for KVM selftests.
Fixes: 3e06cdf10520 ("KVM: selftests: Add initial support for RISC-V
64-bit")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Tested-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'crypto/pcbc.c')
0 files changed, 0 insertions, 0 deletions