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authorThierry Reding2014-04-04 15:55:15 +0200
committerPeter De Schrijver2014-04-17 14:12:46 +0300
commit4ccc402ece35695dd2884ec0b652d52ae0230f13 (patch)
treee72273317bd892e4678ee6ccf776831e863554a1 /drivers/ata/pata_rz1000.c
parentc61e4e75b95bda4c6fec134aa9f08b5629b532e6 (diff)
clk: tegra: Fix enabling of PLLE
When enabling the PLLE as its final step, clk_plle_enable() would accidentally OR in the value previously written to the PLLE_SS_CTRL register. Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/ata/pata_rz1000.c')
0 files changed, 0 insertions, 0 deletions