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authorChristoph Hellwig2017-02-08 00:13:20 +0100
committerJens Axboe2017-02-13 15:43:31 -0700
commitc5c9b26ee5f1295c77d8f2ff5f804ed6c0b07cc4 (patch)
treebdded9c8e3d186cccd0ac22dfc9f056b6bf379b9 /drivers/block/cciss.h
parentecdd09597a57251323b0de50e3d45e69298c4a83 (diff)
cciss: switch to pci_irq_alloc_vectors
Simple cleanup to use the new APIs. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Don Brace <don.brace@microsemi.com> Tested-by: Don Brace <don.brace@microsemi.com> Signed-off-by: Jens Axboe <axboe@fb.com>
Diffstat (limited to 'drivers/block/cciss.h')
-rw-r--r--drivers/block/cciss.h6
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/block/cciss.h b/drivers/block/cciss.h
index 7fda30e4a241..4affa94ca17b 100644
--- a/drivers/block/cciss.h
+++ b/drivers/block/cciss.h
@@ -90,8 +90,6 @@ struct ctlr_info
# define SIMPLE_MODE_INT 2
# define MEMQ_MODE_INT 3
unsigned int intr[4];
- unsigned int msix_vector;
- unsigned int msi_vector;
int intr_mode;
int cciss_max_sectors;
BYTE cciss_read;
@@ -333,7 +331,7 @@ static unsigned long SA5_performant_completed(ctlr_info_t *h)
*/
register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
/* msi auto clears the interrupt pending bit. */
- if (!(h->msi_vector || h->msix_vector)) {
+ if (!(h->pdev->msi_enabled || h->pdev->msix_enabled)) {
writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
/* Do a read in order to flush the write to the controller
* (as per spec.)
@@ -393,7 +391,7 @@ static bool SA5_performant_intr_pending(ctlr_info_t *h)
if (!register_value)
return false;
- if (h->msi_vector || h->msix_vector)
+ if (h->pdev->msi_enabled || h->pdev->msix_enabled)
return true;
/* Read outbound doorbell to flush */