diff options
| author | Lorenzo Pieralisi | 2012-07-13 15:55:52 +0100 |
|---|---|---|
| committer | Nicolas Pitre | 2013-05-29 15:50:34 -0400 |
| commit | ed69bdd8fd9b2db68b915ce5f60fc51d4744a9b1 (patch) | |
| tree | 02dc3a5343f662ce153c66cb0e370a49b35b066f /drivers/bus/Kconfig | |
| parent | 78ecad0183bd7e49131da2b5aa82bee017db1cf0 (diff) | |
drivers: bus: add ARM CCI support
On ARM multi-cluster systems coherency between cores running on
different clusters is managed by the cache-coherent interconnect (CCI).
It allows broadcasting of TLB invalidates and memory barriers and it
guarantees cache coherency at system level through snooping of slave
interfaces connected to it.
This patch enables the basic infrastructure required in Linux to handle and
programme the CCI component.
Non-local variables used by the CCI management functions called by power
down function calls after disabling the cache must be flushed out to main
memory in advance, otherwise incoherency of those values may occur if they
are sitting in the cache of some other CPU when power down functions
execute. Driver code ensures that relevant data structures are flushed
from inner and outer caches after the driver probe is completed.
CCI slave port resources are linked to set of CPUs through bus masters
phandle properties that link the interface resources to masters node in
the device tree.
Documentation describing the CCI DT bindings is provided with the patch.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Diffstat (limited to 'drivers/bus/Kconfig')
| -rw-r--r-- | drivers/bus/Kconfig | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index b05ecab915c4..5286e2d333b0 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -26,4 +26,11 @@ config OMAP_INTERCONNECT help Driver to enable OMAP interconnect error handling driver. + +config ARM_CCI + bool "ARM CCI driver support" + depends on ARM + help + Driver supporting the CCI cache coherent interconnect for ARM + platforms. endmenu |