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author | Bill Huang | 2015-06-18 17:28:39 -0400 |
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committer | Thierry Reding | 2015-12-17 13:37:58 +0100 |
commit | 2d7f61f37731f635af47615a8a331ffe7f884934 (patch) | |
tree | 57424c3745bc493aca9837f77d97ec8335bbea7f /drivers/clk/clk-axm5516.c | |
parent | a4ca2b2fe7252032022d14b4efd462161c91165b (diff) |
clk: tegra: Read correct IDDQ register in PLL_SS registration
This fixes a bug in tegra_clk_register_pllss() which mistakenly assume
the IDDQ register is the PLL base address.
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/clk-axm5516.c')
0 files changed, 0 insertions, 0 deletions