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authorLeo Yan2017-01-21 10:26:31 +0800
committerStephen Boyd2017-01-26 16:18:34 -0800
commit55da97e38cab844682abb71400a908b871d0054c (patch)
tree2803c0d3fa402c7d577d294761a2ba4cd1815511 /drivers/clk/hisilicon/clkgate-separated.c
parentde9b5a24047d50490ff58428bd1dc8bc4b63a225 (diff)
clk: hisilicon: fix lock assignment
In clock driver initialize phase the spinlock is missed to assignment to struct clkgate_separated, finally there have no locking to protect exclusive accessing for clock registers. This bug introduces the console has no output after enable coresight driver on 96boards Hikey; this is because console using UART3, which has shared the same register with coresight clock enabling bit. After applied this patch it can assign lock properly to protect exclusive accessing, and console can work well after enabled coresight modules. Fixes: 0aa0c95f743a ("clk: hisilicon: add common clock support") Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/hisilicon/clkgate-separated.c')
-rw-r--r--drivers/clk/hisilicon/clkgate-separated.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/hisilicon/clkgate-separated.c b/drivers/clk/hisilicon/clkgate-separated.c
index a47812f56a17..7908bc3c9ec7 100644
--- a/drivers/clk/hisilicon/clkgate-separated.c
+++ b/drivers/clk/hisilicon/clkgate-separated.c
@@ -120,6 +120,7 @@ struct clk *hisi_register_clkgate_sep(struct device *dev, const char *name,
sclk->bit_idx = bit_idx;
sclk->flags = clk_gate_flags;
sclk->hw.init = &init;
+ sclk->lock = lock;
clk = clk_register(dev, &sclk->hw);
if (IS_ERR(clk))