diff options
| author | Abel Vesa | 2019-02-15 17:48:43 +0000 |
|---|---|---|
| committer | Stephen Boyd | 2019-02-21 12:56:52 -0800 |
| commit | ad18bbf369a6a49633f50be4d1bcc9b5aad422fc (patch) | |
| tree | 70f5219339e16c3940f571dddf1108a6b3d52bc1 /drivers/clk/imx | |
| parent | 202ce5afe51e883f94736310997ea1c73219eb36 (diff) | |
clk: imx: imx8mq: Fix the rate propagation for arm pll
The arm pll bypass needs to propagate the rate upwards
in order for the cpufreq to work.
Fixes: b80522040cd3f ("clk: imx: Add clock driver for i.MX8MQ CCM")
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/imx')
| -rw-r--r-- | drivers/clk/imx/clk-imx8mq.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index 897740f0a012..90986ddc0f37 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -345,7 +345,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) clks[IMX8MQ_DRAM_PLL2_DIV] = imx_clk_divider("dram_pll2_div", "dram_pll2", base + 0x68, 1, 6); /* PLL bypass out */ - clks[IMX8MQ_ARM_PLL_BYPASS] = imx_clk_mux("arm_pll_bypass", base + 0x28, 14, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels)); + clks[IMX8MQ_ARM_PLL_BYPASS] = imx_clk_mux_flags("arm_pll_bypass", base + 0x28, 14, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT); clks[IMX8MQ_GPU_PLL_BYPASS] = imx_clk_mux("gpu_pll_bypass", base + 0x18, 14, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels)); clks[IMX8MQ_VPU_PLL_BYPASS] = imx_clk_mux("vpu_pll_bypass", base + 0x20, 14, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels)); clks[IMX8MQ_AUDIO_PLL1_BYPASS] = imx_clk_mux("audio_pll1_bypass", base + 0x0, 14, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels)); |