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authorGuoniu.zhou2021-06-04 17:09:35 +0800
committerAbel Vesa2021-06-14 12:34:14 +0300
commitb192d04011ee7dadfa3045beae4a2ef7dd71d027 (patch)
tree65d443d87a9d0380ad3cf4a8aa2b5b86038eba14 /drivers/clk/imx
parentbabfaa9556d7a9df2784bfcddafdeba29d24c8fd (diff)
clk: imx: scu: add parallel port clock ops
Because digital pll for parallel interface is on by default, and not provide enable/disable function by scu, so add the related ops for this kind of clocks. Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Diffstat (limited to 'drivers/clk/imx')
-rw-r--r--drivers/clk/imx/clk-scu.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c
index f4efb3b76c86..680b2650fd45 100644
--- a/drivers/clk/imx/clk-scu.c
+++ b/drivers/clk/imx/clk-scu.c
@@ -425,6 +425,12 @@ static const struct clk_ops clk_scu_cpu_ops = {
.unprepare = clk_scu_unprepare,
};
+static const struct clk_ops clk_scu_pi_ops = {
+ .recalc_rate = clk_scu_recalc_rate,
+ .round_rate = clk_scu_round_rate,
+ .set_rate = clk_scu_set_rate,
+};
+
struct clk_hw *__imx_clk_scu(struct device *dev, const char *name,
const char * const *parents, int num_parents,
u32 rsrc_id, u8 clk_type)
@@ -445,6 +451,8 @@ struct clk_hw *__imx_clk_scu(struct device *dev, const char *name,
init.ops = &clk_scu_ops;
if (rsrc_id == IMX_SC_R_A35)
init.ops = &clk_scu_cpu_ops;
+ else if (rsrc_id == IMX_SC_R_PI_0_PLL)
+ init.ops = &clk_scu_pi_ops;
else
init.ops = &clk_scu_ops;
init.parent_names = parents;