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authorShunli Wang2016-11-04 15:43:05 +0800
committerStephen Boyd2016-11-08 15:59:49 -0800
commite9862118272aa528e35e54ef9f1e35c217870fd7 (patch)
tree8dc89a1e94dfef635dab7ac98d423cda5247627a /drivers/clk/mediatek/clk-gate.h
parente0a3862c14f80e34d5787f1e038601da8ff9cc77 (diff)
clk: mediatek: Add MT2701 clock support
Add MT2701 clock support, include topckgen, apmixedsys, infracfg, pericfg and subsystem clocks. Signed-off-by: Shunli Wang <shunli.wang@mediatek.com> Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Erin Lo <erin.lo@mediatek.com> Tested-by: John Crispin <blogic@openwrt.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-gate.h')
-rw-r--r--drivers/clk/mediatek/clk-gate.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h
index b1821603b887..72ef89b3ad7b 100644
--- a/drivers/clk/mediatek/clk-gate.h
+++ b/drivers/clk/mediatek/clk-gate.h
@@ -36,6 +36,8 @@ static inline struct mtk_clk_gate *to_mtk_clk_gate(struct clk_hw *hw)
extern const struct clk_ops mtk_clk_gate_ops_setclr;
extern const struct clk_ops mtk_clk_gate_ops_setclr_inv;
+extern const struct clk_ops mtk_clk_gate_ops_no_setclr;
+extern const struct clk_ops mtk_clk_gate_ops_no_setclr_inv;
struct clk *mtk_clk_register_gate(
const char *name,