diff options
| author | Weiyi Lu | 2019-03-05 13:05:45 +0800 |
|---|---|---|
| committer | Stephen Boyd | 2019-04-11 13:29:19 -0700 |
| commit | acddfc2c261b3653ab1c1b567a427299bac20d31 (patch) | |
| tree | bdacafd8bc6ece8d1219198e7eb9d4fec6743a9e /drivers/clk/mediatek/clk-mt8183-img.c | |
| parent | 23fe31dedb7b1836cc23666afc1a9c67ed7de775 (diff) | |
clk: mediatek: Add MT8183 clock support
Add MT8183 clock support, include topckgen, apmixedsys,
infracfg, mcucfg and subsystem clocks.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-mt8183-img.c')
| -rw-r--r-- | drivers/clk/mediatek/clk-mt8183-img.c | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/drivers/clk/mediatek/clk-mt8183-img.c b/drivers/clk/mediatek/clk-mt8183-img.c new file mode 100644 index 000000000000..470d676a4a10 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8183-img.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2018 MediaTek Inc. +// Author: Weiyi Lu <weiyi.lu@mediatek.com> + +#include <linux/clk-provider.h> +#include <linux/platform_device.h> + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include <dt-bindings/clock/mt8183-clk.h> + +static const struct mtk_gate_regs img_cg_regs = { + .set_ofs = 0x4, + .clr_ofs = 0x8, + .sta_ofs = 0x0, +}; + +#define GATE_IMG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate img_clks[] = { + GATE_IMG(CLK_IMG_LARB5, "img_larb5", "img_sel", 0), + GATE_IMG(CLK_IMG_LARB2, "img_larb2", "img_sel", 1), + GATE_IMG(CLK_IMG_DIP, "img_dip", "img_sel", 2), + GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "img_sel", 3), + GATE_IMG(CLK_IMG_DPE, "img_dpe", "img_sel", 4), + GATE_IMG(CLK_IMG_RSC, "img_rsc", "img_sel", 5), + GATE_IMG(CLK_IMG_MFB, "img_mfb", "img_sel", 6), + GATE_IMG(CLK_IMG_WPE_A, "img_wpe_a", "img_sel", 7), + GATE_IMG(CLK_IMG_WPE_B, "img_wpe_b", "img_sel", 8), + GATE_IMG(CLK_IMG_OWE, "img_owe", "img_sel", 9), +}; + +static int clk_mt8183_img_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + + clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK); + + mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks), + clk_data); + + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); +} + +static const struct of_device_id of_match_clk_mt8183_img[] = { + { .compatible = "mediatek,mt8183-imgsys", }, + {} +}; + +static struct platform_driver clk_mt8183_img_drv = { + .probe = clk_mt8183_img_probe, + .driver = { + .name = "clk-mt8183-img", + .of_match_table = of_match_clk_mt8183_img, + }, +}; + +builtin_platform_driver(clk_mt8183_img_drv); |