diff options
| author | Joe.C | 2015-07-13 17:32:48 +0800 |
|---|---|---|
| committer | James Liao | 2015-10-01 12:04:34 +0800 |
| commit | 2d61fe0fc7f0a8c214587ba063fc8770486c0af1 (patch) | |
| tree | eb39ce09b0e3f102da7f522930100152e2f86023 /drivers/clk/mediatek | |
| parent | 9ffecb10283508260936b96022d4ee43a7798b4c (diff) | |
clk: mediatek: add 13mhz clock for MT8173
Add 13mhz clock used by GPT timer in infracfg.
Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Diffstat (limited to 'drivers/clk/mediatek')
| -rw-r--r-- | drivers/clk/mediatek/clk-mt8173.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c index 90eff85f4285..9ea6aa1f30d5 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -619,6 +619,10 @@ static const struct mtk_gate infra_clks[] __initconst = { GATE_ICG(CLK_INFRA_PMICWRAP, "infra_pmicwrap", "axi_sel", 23), }; +static const struct mtk_fixed_factor infra_divs[] __initconst = { + FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2), +}; + static const struct mtk_gate_regs peri0_cg_regs = { .set_ofs = 0x0008, .clr_ofs = 0x0010, @@ -754,6 +758,7 @@ static void __init mtk_infrasys_init(struct device_node *node) mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), clk_data); + mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); if (r) |