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author | Raju Lakkaraju | 2016-10-03 12:53:13 +0530 |
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committer | David S. Miller | 2016-10-04 00:47:30 -0400 |
commit | a4cc96d1f0170b779c32c6b2cc58764f5d2cdef0 (patch) | |
tree | 1360a3ab54480f50ba3f6660e9eb8fdbe2af6ba4 /drivers/clk/meson/clk-pll.c | |
parent | 277964e19e1416ca31301e113edb2580c81a8b66 (diff) |
net: phy: Add Edge-rate driver for Microsemi PHYs.
Edge-rate:
As system and networking speeds increase, a signal's output transition,
also know as the edge rate or slew rate (V/ns), takes on greater importance
because high-speed signals come with a price. That price is an assortment of
interference problems like ringing on the line, signal overshoot and
undershoot, extended signal settling times, crosstalk noise, transmission
line reflections, false signal detection by the receiving device and
electromagnetic interference (EMI) -- all of which can negate the potential
gains designers are seeking when they try to increase system speeds through
the use of higher performance logic devices. The fact is, faster signaling
edge rates can cause a higher level of electrical noise or other type of
interference that can actually lead to slower line speeds and lower maximum
system frequencies. This parameter allow the board designers to change the
driving strange, and thereby change the EMI behavioral.
Edge-rate parameters (vddmac, edge-slowdown) get from Device Tree.
Tested on Beaglebone Black with VSC 8531 PHY.
Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@microsemi.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/clk/meson/clk-pll.c')
0 files changed, 0 insertions, 0 deletions