diff options
| author | Neil Armstrong | 2017-08-01 13:56:59 +0200 |
|---|---|---|
| committer | Neil Armstrong | 2017-08-04 18:02:02 +0200 |
| commit | 62ec0b9754aced0b4c02694886cbe9bfd3d00f2f (patch) | |
| tree | 8fda35ec7e8dcfd3f1d55cc405290a66b8e3a958 /drivers/clk/meson/gxbb-aoclk.h | |
| parent | ffb13e3b84f4619ec6a4ca61a6cedf2d50858949 (diff) | |
clk: meson: gxbb-aoclk: Add CEC 32k clock
The CEC 32K AO Clock is a dual divider with dual counter to provide a more
precise 32768Hz clock for the CEC subsystem from the external xtal.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/gxbb-aoclk.h')
| -rw-r--r-- | drivers/clk/meson/gxbb-aoclk.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/clk/meson/gxbb-aoclk.h b/drivers/clk/meson/gxbb-aoclk.h index 2e26108d5ba6..e8604c8f7eee 100644 --- a/drivers/clk/meson/gxbb-aoclk.h +++ b/drivers/clk/meson/gxbb-aoclk.h @@ -9,7 +9,13 @@ #define __GXBB_AOCLKC_H /* AO Configuration Clock registers offsets */ +#define AO_RTI_PWR_CNTL_REG1 0x0c +#define AO_RTI_PWR_CNTL_REG0 0x10 #define AO_RTI_GEN_CNTL_REG0 0x40 +#define AO_OSCIN_CNTL 0x58 +#define AO_CRT_CLK_CNTL1 0x68 +#define AO_RTC_ALT_CLK_CNTL0 0x94 +#define AO_RTC_ALT_CLK_CNTL1 0x98 struct aoclk_gate_regmap { struct clk_hw hw; @@ -23,4 +29,14 @@ struct aoclk_gate_regmap { extern const struct clk_ops meson_aoclk_gate_regmap_ops; +struct aoclk_cec_32k { + struct clk_hw hw; + struct regmap *regmap; + spinlock_t *lock; +}; + +#define to_aoclk_cec_32k(_hw) container_of(_hw, struct aoclk_cec_32k, hw) + +extern const struct clk_ops meson_aoclk_cec_32k_ops; + #endif /* __GXBB_AOCLKC_H */ |