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authorPeter De Schrijver2013-04-03 17:40:39 +0300
committerStephen Warren2013-04-04 16:10:45 -0600
commit0b6525acd13f2d33cd3be86d0dbd2ddd1ffeda8f (patch)
tree989c920b532d4d5d7372c275ed828356cff9c581 /drivers/clk/mxs
parent7ba28813b41120dd67329fd04dc732ea7fef05a0 (diff)
clk: tegra: Add PLL post divider table
Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider. Introduce a table based approach and switch PLLU to it. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'drivers/clk/mxs')
0 files changed, 0 insertions, 0 deletions