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authorStephen Boyd2018-08-14 17:42:29 +0530
committerStephen Boyd2018-10-17 13:14:59 -0700
commitbb5c4a85051e5e0be39c775b6df85521f2ae807d (patch)
tree702f6aae2a1f2faf3660fc5012aaed35a8b6a494 /drivers/clk/qcom/clk-krait.c
parent40e5ddf4f84869815129551f4a8cfc2c223ebeae (diff)
clk: qcom: Add Krait clock controller driver
The Krait CPU clocks are made up of a primary mux and secondary mux for each CPU and the L2, controlled via cp15 accessors. For Kraits within KPSSv1 each secondary mux accepts a different aux source, but on KPSSv2 each secondary mux accepts the same aux source. Cc: <devicetree@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Tested-by: Craig Tatlor <ctatlor97@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/qcom/clk-krait.c')
-rw-r--r--drivers/clk/qcom/clk-krait.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c
index 2e417678029f..7ede744c6a14 100644
--- a/drivers/clk/qcom/clk-krait.c
+++ b/drivers/clk/qcom/clk-krait.c
@@ -44,7 +44,7 @@ static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
struct krait_mux_clk *mux = to_krait_mux_clk(hw);
u32 sel;
- sel = clk_mux_reindex(index, mux->parent_map, 0);
+ sel = clk_mux_index_to_val(mux->parent_map, 0, index);
mux->en_mask = sel;
/* Don't touch mux if CPU is off as it won't work */
if (__clk_is_enabled(hw->clk))
@@ -63,7 +63,7 @@ static u8 krait_mux_get_parent(struct clk_hw *hw)
sel &= mux->mask;
mux->en_mask = sel;
- return clk_mux_get_parent(hw, sel, mux->parent_map, 0);
+ return clk_mux_val_to_index(hw, mux->parent_map, 0, sel);
}
const struct clk_ops krait_mux_clk_ops = {