diff options
| author | Simon Horman | 2019-03-25 17:35:51 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven | 2019-04-02 09:50:48 +0200 |
| commit | 10d9ea5100c89afd677a202036e0e34e129a6c52 (patch) | |
| tree | 8d2e6c4f2701568ac3b13048556dc89989a4be26 /drivers/clk/renesas/r8a774a1-cpg-mssr.c | |
| parent | 20cc05ba04a93f05d6c50789fe35d762a2db4e96 (diff) | |
clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset
Parameterise the offset of control bits within the FRQCRC register
for Z and Z2 clocks.
This is in preparation for supporting the Z2 clock on the R-Car E3
(r8a77990) SoC which uses a different offset for control bits to
other, already, supported SoCs.
As suggested by Geert Uytterhoeven.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/r8a774a1-cpg-mssr.c')
| -rw-r--r-- | drivers/clk/renesas/r8a774a1-cpg-mssr.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c index 99bcb7c8022f..8e7bb43b6848 100644 --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c @@ -71,8 +71,8 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */ - DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2), - DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2), + DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), + DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2, 0), DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1), |