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authorChristophe JAILLET2020-04-13 06:17:09 +0200
committerGeert Uytterhoeven2020-04-14 09:22:16 +0200
commitcdfdeb4a381d97d441ac421a86a2e8158346ad51 (patch)
tree6fee8649a30f7a2bd89eb30562dc99f226eb9674 /drivers/clk/renesas
parent91a577e77fdf55bdc6cd863581658761908c1686 (diff)
clk: renesas: r9a06g032: Fix some typo in comments
This file seems to be for R9A06G032 only. So replace reference to R9A09G032 by R9A06G032 to avoid confusion. AFAIK, R9A09G032 does'nt exist. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/20200413041709.3630-1-christophe.jaillet@wanadoo.fr Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas')
-rw-r--r--drivers/clk/renesas/r9a06g032-clocks.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c
index 1907ee195a08..d900f6bf53d0 100644
--- a/drivers/clk/renesas/r9a06g032-clocks.c
+++ b/drivers/clk/renesas/r9a06g032-clocks.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * R9A09G032 clock driver
+ * R9A06G032 clock driver
*
* Copyright (C) 2018 Renesas Electronics Europe Limited
*
@@ -338,8 +338,8 @@ clk_rdesc_get(struct r9a06g032_priv *clocks,
}
/*
- * This implements the R9A09G032 clock gate 'driver'. We cannot use the system's
- * clock gate framework as the gates on the R9A09G032 have a special enabling
+ * This implements the R9A06G032 clock gate 'driver'. We cannot use the system's
+ * clock gate framework as the gates on the R9A06G032 have a special enabling
* sequence, therefore we use this little proxy.
*/
struct r9a06g032_clk_gate {