diff options
| author | Sylwester Nawrocki | 2018-02-12 16:52:27 +0100 |
|---|---|---|
| committer | Sylwester Nawrocki | 2018-02-14 16:01:33 +0100 |
| commit | 83942bdd992ff347442ec72d86c2d77fe51a0270 (patch) | |
| tree | a841d2293fdd37c3b71442569f30cee5ed004ffe /drivers/clk/samsung | |
| parent | 5c7979246ead98a7269f418d81a637dd056a1be7 (diff) | |
clk: exynos5433: Extend list of available AUD_PLL output frequencies
Add one more entry to the exynos5433_aud_pll_rates table, this allows
to support audio sample rates: 48000, 96000, 192000 Hz with minimum
error. The M, P, S, K values re confirmed by the HW team.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Diffstat (limited to 'drivers/clk/samsung')
| -rw-r--r-- | drivers/clk/samsung/clk-exynos5433.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index c84326dc4b05..57a41824ee2e 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -765,6 +765,7 @@ static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] __initcons PLL_36XX_RATE(294912000U, 98, 1, 3, 19923), PLL_36XX_RATE(288000000U, 96, 1, 3, 0), PLL_36XX_RATE(252000000U, 84, 1, 3, 0), + PLL_36XX_RATE(196608001U, 197, 3, 3, -25690), { /* sentinel */ } }; |