diff options
author | Chen-Yu Tsai | 2017-12-08 16:35:10 +0800 |
---|---|---|
committer | Maxime Ripard | 2017-12-08 10:08:07 +0100 |
commit | 7d333ef1cc1b8c8951f3a2c41f6406e2295d8be9 (patch) | |
tree | fe53d1a1e2a6ba5b08691018ee13b293825350a6 /drivers/clk/sunxi-ng/ccu_nm.h | |
parent | 83fe3be4d1974f5f50c5e2039a1609f4960e8579 (diff) |
clk: sunxi-ng: Support fixed post-dividers on NM style clocks
On the A83T, the audio PLL should have its div1 set to 0, or /1, and
div2 set to 1, or /2. This setting is the default, and is required
to match the sigma-delta modulation parameters from the BSP kernel.
To do this, we first add fixed post-divider to the NM style clocks,
which is the type of clock the audio PLL clock is modeled into.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/clk/sunxi-ng/ccu_nm.h')
-rw-r--r-- | drivers/clk/sunxi-ng/ccu_nm.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/sunxi-ng/ccu_nm.h b/drivers/clk/sunxi-ng/ccu_nm.h index c623b0c7a23c..eba586b4c7d0 100644 --- a/drivers/clk/sunxi-ng/ccu_nm.h +++ b/drivers/clk/sunxi-ng/ccu_nm.h @@ -36,6 +36,8 @@ struct ccu_nm { struct ccu_frac_internal frac; struct ccu_sdm_internal sdm; + unsigned int fixed_post_div; + struct ccu_common common; }; |