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authorChen-Yu Tsai2017-07-23 18:27:44 +0800
committerChen-Yu Tsai2017-08-04 12:05:20 +0800
commit48d5eb619c15847aba6757deb5c2c8badca2aece (patch)
tree1ee0062ccdb17d96195707cd3fbe1761269068b8 /drivers/clk/sunxi-ng/ccu_phase.c
parent1d42460a49347af4d1db345197e5d1277336b312 (diff)
clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change
This patch utilizes the new PLL clk notifier to gate then ungate the PLL CPU clock after rate changes. This should prevent any system hangs resulting from cpufreq changes to the clk. Reported-by: Ondrej Jirman <megous@megous.com> Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/sunxi-ng/ccu_phase.c')
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