aboutsummaryrefslogtreecommitdiff
path: root/drivers/clk/tegra/clk-pll.c
diff options
context:
space:
mode:
authorStephen Boyd2019-05-07 11:44:56 -0700
committerStephen Boyd2019-05-07 11:44:56 -0700
commit7e9c62bdb41af76974d594da89854a6aba645e58 (patch)
tree835f8585e025810a0e015d9172f43cdf7e2749e7 /drivers/clk/tegra/clk-pll.c
parentf6111b9d7970df07f783d3891735003fef2bc37e (diff)
parent7fbb639aea353832046a72ad3201510cada27f9a (diff)
parentdefb149ba42f571017fb4bc265eecf3648ab7d6e (diff)
parentaa2a0592ceb65bcba5fa1b8d9a7fb8c43d7cadb9 (diff)
parenteaa9558d35aee594c9658d92852e537a0fb897d7 (diff)
parent5852b1365df4414523210e444ac7df1dec09acb4 (diff)
Merge branches 'clk-sa', 'clk-aspeed', 'clk-samsung', 'clk-ingenic' and 'clk-zynq' into clk-next
- Various static analysis fixes/finds - Video Engine (ECLK) support on Aspeed SoCs - Xilinx ZynqMP Versal platform support - Convert Xilinx ZynqMP driver to be struct oriented * clk-sa: clk: mvebu: fix spelling mistake "gatable" -> "gateable" clk: ux500: add range to usleep_range clk: tegra: Make tegra_clk_super_mux_ops static clk: davinci: cfgchip: use PTR_ERR_OR_ZERO in da8xx_cfgchip_register_div4p5 * clk-aspeed: clk: Aspeed: Setup video engine clocking * clk-samsung: clk: samsung: exynos5410: Add gate clock for ADC clk: samsung: dt-bindings: Add ADC clock ID to Exynos5410 clk: samsung: dt-bindings: Put CLK_UART3 in order * clk-ingenic: clk: ingenic: jz4725b: Add UDC PHY clock dt-bindings: clock: jz4725b-cgu: Add UDC PHY clock * clk-zynq: clk: zynqmp: use structs for clk query responses clk: zynqmp: fix check for fractional clock clk: zynqmp: do not export zynqmp_clk_register_* functions clk: zynqmp: fix kerneldoc of __zynqmp_clock_get_parents drivers: clk: Update clock driver to handle clock attribute drivers: clk: zynqmp: Allow zero divisor value