diff options
| author | Mikko Perttunen | 2015-09-15 12:55:15 +0300 |
|---|---|---|
| committer | Thierry Reding | 2015-09-15 12:54:39 +0200 |
| commit | 10d9be6ebe9199feb7680433a24b564a31a8f9b1 (patch) | |
| tree | 16a3843c12fcd7c9e9dc75ee49dd57dd525fc650 /drivers/clk/tegra/cvb.c | |
| parent | 6ff33f3902c3b1c5d0db6b1e2c70b6d76fba357f (diff) | |
clk: tegra: Unlock top rates for Tegra124 DFLL clock
The new determine_rate prototype allows for clock rates exceeding
2^31-1 Hz to be used. Switch the DFLL clock to use determine_rate
instead of round_rate and unlock the top rates supported by the
Tegra124.
Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/cvb.c')
| -rw-r--r-- | drivers/clk/tegra/cvb.c | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/drivers/clk/tegra/cvb.c b/drivers/clk/tegra/cvb.c index 0204e0861134..69c74eec3a4b 100644 --- a/drivers/clk/tegra/cvb.c +++ b/drivers/clk/tegra/cvb.c @@ -78,13 +78,6 @@ static int build_opp_table(const struct cvb_table *d, if (!table->freq || (table->freq > max_freq)) break; - /* - * FIXME after clk_round_rate/clk_determine_rate prototypes - * have been updated - */ - if (table->freq & (1<<31)) - continue; - dfll_mv = get_cvb_voltage( speedo_value, d->speedo_scale, &table->coefficients); dfll_mv = round_cvb_voltage(dfll_mv, d->voltage_scale, align); |