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authorEugeniy Paltsev2020-03-11 16:41:15 +0300
committerStephen Boyd2020-05-28 21:06:39 -0700
commit56fbeefe366e5920802f60f26b6b59b365c0569b (patch)
tree6c89a056b78a8189ce5d9518978d096a691c1853 /drivers/clk
parent423f042a65a2af82337af4e3c7f2cd828185e4f3 (diff)
CLK: HSDK: CGU: add support for 148.5MHz clock
Add support for 148.5MHz clock for HDMI PLL Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Link: https://lkml.kernel.org/r/20200311134115.13257-4-Eugeniy.Paltsev@synopsys.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/clk-hsdk-pll.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c
index 0ea7af57a5b1..b4f8852201cb 100644
--- a/drivers/clk/clk-hsdk-pll.c
+++ b/drivers/clk/clk-hsdk-pll.c
@@ -81,6 +81,7 @@ static const struct hsdk_pll_cfg asdt_pll_cfg[] = {
static const struct hsdk_pll_cfg hdmi_pll_cfg[] = {
{ 27000000, 0, 0, 0, 0, 1 },
+ { 148500000, 0, 21, 3, 0, 0 },
{ 297000000, 0, 21, 2, 0, 0 },
{ 540000000, 0, 19, 1, 0, 0 },
{ 594000000, 0, 21, 1, 0, 0 },