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author | Heiko Stuebner | 2015-06-18 16:18:31 +0200 |
---|---|---|
committer | Stephen Boyd | 2015-07-06 15:03:25 -0700 |
commit | 6f085072534363b68c705d54b9dbbed0474ff357 (patch) | |
tree | 3ebff805634a9a7cd071ace2d699d91ce03f4f93 /drivers/clk | |
parent | 2d7884a7d0e70f9509881c40eaee3f5a5c201b07 (diff) |
clk: rockchip: add COMPOSITE_NOGATE_DIVTBL variant
A clock branch consisting of a mux and divider with non-standard
divider values.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r-- | drivers/clk/rockchip/clk.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 92edb5f9e7e8..501f02ea9d4b 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -308,6 +308,26 @@ struct rockchip_clk_branch { .gate_offset = -1, \ } +#define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms, \ + mw, mf, ds, dw, df, dt) \ + { \ + .id = _id, \ + .branch_type = branch_composite, \ + .name = cname, \ + .parent_names = pnames, \ + .num_parents = ARRAY_SIZE(pnames), \ + .flags = f, \ + .muxdiv_offset = mo, \ + .mux_shift = ms, \ + .mux_width = mw, \ + .mux_flags = mf, \ + .div_shift = ds, \ + .div_width = dw, \ + .div_flags = df, \ + .div_table = dt, \ + .gate_offset = -1, \ + } + #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\ { \ .id = _id, \ |