diff options
| author | Michael Turquette | 2016-07-05 17:16:08 -0700 |
|---|---|---|
| committer | Michael Turquette | 2016-07-06 01:25:08 -0700 |
| commit | 9d6928639134cff896a92f8ff7fad14370e88d3c (patch) | |
| tree | c69ca3c4e3cb43b28cadb57d8ec35e92893b31a0 /drivers/clk | |
| parent | 086347705be7530feabb6274a3ad81dd545e7914 (diff) | |
| parent | 9ca91a65583c73e4be6e9f53323a7ae04e6803ef (diff) | |
Merge tag 'sunxi-clk-fixes-for-4.7' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-fixes
Allwinner clock fixes for 4.7
A bunch of changes for the display clocks merged in 4.7
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/sunxi/clk-sun4i-display.c | 5 | ||||
| -rw-r--r-- | drivers/clk/sunxi/clk-sun4i-tcon-ch1.c | 4 |
2 files changed, 4 insertions, 5 deletions
diff --git a/drivers/clk/sunxi/clk-sun4i-display.c b/drivers/clk/sunxi/clk-sun4i-display.c index 445a7498d6df..9780fac6d029 100644 --- a/drivers/clk/sunxi/clk-sun4i-display.c +++ b/drivers/clk/sunxi/clk-sun4i-display.c @@ -33,6 +33,8 @@ struct sun4i_a10_display_clk_data { u8 width_div; u8 width_mux; + + u32 flags; }; struct reset_data { @@ -166,7 +168,7 @@ static void __init sun4i_a10_display_init(struct device_node *node, data->has_div ? &div->hw : NULL, data->has_div ? &clk_divider_ops : NULL, &gate->hw, &clk_gate_ops, - 0); + data->flags); if (IS_ERR(clk)) { pr_err("%s: Couldn't register the clock\n", clk_name); goto free_div; @@ -232,6 +234,7 @@ static const struct sun4i_a10_display_clk_data sun4i_a10_tcon_ch0_data __initcon .offset_rst = 29, .offset_mux = 24, .width_mux = 2, + .flags = CLK_SET_RATE_PARENT, }; static void __init sun4i_a10_tcon_ch0_setup(struct device_node *node) diff --git a/drivers/clk/sunxi/clk-sun4i-tcon-ch1.c b/drivers/clk/sunxi/clk-sun4i-tcon-ch1.c index 98a4582de56a..b6d29d1bedca 100644 --- a/drivers/clk/sunxi/clk-sun4i-tcon-ch1.c +++ b/drivers/clk/sunxi/clk-sun4i-tcon-ch1.c @@ -79,15 +79,11 @@ static int tcon_ch1_is_enabled(struct clk_hw *hw) static u8 tcon_ch1_get_parent(struct clk_hw *hw) { struct tcon_ch1_clk *tclk = hw_to_tclk(hw); - int num_parents = clk_hw_get_num_parents(hw); u32 reg; reg = readl(tclk->reg) >> TCON_CH1_SCLK2_MUX_SHIFT; reg &= reg >> TCON_CH1_SCLK2_MUX_MASK; - if (reg >= num_parents) - return -EINVAL; - return reg; } |