diff options
| author | Lucas Stach | 2016-02-29 21:46:06 +0100 |
|---|---|---|
| committer | Thierry Reding | 2016-04-28 12:41:51 +0200 |
| commit | a02cc84a31d3bd46a10546ff7024e7b5a186d339 (patch) | |
| tree | cf51407240888a2c212593cd89541e97ba88a014 /drivers/clk | |
| parent | 926655f929063619b13db8b4f2ef8c9a08605492 (diff) | |
clk: tegra: Initialize PLL_C to sane rate on Tegra30
If the bootloader does not touch PLL_C it will stay in its reset state,
failing to lock when enabled. This leads to consumers of this clock to
fail probing. Fix this by always programming the PLL with a sane rate,
which allows it to lock, at startup.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra30.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 0478565cf292..236e2db9a716 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -1372,6 +1372,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0 }, { TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0 }, { TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0 }, + { TEGRA30_CLK_PLL_C, TEGRA30_CLK_CLK_MAX, 600000000, 0 }, { TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0 }, { TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0 }, { TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0 }, |