diff options
| author | Heiko Stuebner | 2019-06-06 10:05:40 +0200 |
|---|---|---|
| committer | Heiko Stuebner | 2019-06-14 18:56:07 +0200 |
| commit | b3b723d8c485af81663b5331459885536006d7fa (patch) | |
| tree | 04fe0bc7dbab1a9441c3d21531fb63dbfdfd942d /drivers/clk | |
| parent | 7d2129310b8c1f22850d56b1725447aef88d8b1f (diff) | |
clk: rockchip: add a type from SGRF-controlled gate clocks
Some clk gates on Rockchip SoCs are part of the SGRF (secure general
register files) and thus only controllable from secure mode, with the
most prominent example being the watchdog.
In most cases we still want to define this as a real clock though,
to have complete clock tree and not reference the generic base-clock
from the devicetree.
So far we've just defined this as factor-1-1 clocks in the clock init,
so define a special clock-type for it so that this definition can be
part of the general tree-definition and save some boilerplate code.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/rockchip/clk.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 1b5270755431..2a911923cf81 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -820,6 +820,10 @@ struct rockchip_clk_branch { .gate_offset = -1, \ } +/* SGRF clocks are only accessible from secure mode, so not controllable */ +#define SGRF_GATE(_id, cname, pname) \ + FACTOR(_id, cname, pname, 0, 1, 1) + struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np, void __iomem *base, unsigned long nr_clks); void rockchip_clk_of_add_provider(struct device_node *np, |