diff options
| author | Gregory CLEMENT | 2014-09-02 10:15:19 +0200 |
|---|---|---|
| committer | Jason Cooper | 2014-09-09 15:15:22 +0000 |
| commit | ceac26c64200015a5e6e358e903b1ca9a6f41dd8 (patch) | |
| tree | 16747d62ac7debefb433bc8985ebe7f4c77edbf6 /drivers/clk | |
| parent | 5e1a63f5f548bb8a3967f00be2f0e1e04290c613 (diff) | |
clk: mvebu: armada-375: Fix the description of the SAR in the comment
For dealing with the code we use the SAR1 and not the SAR0. The code
was correct, and now the comments too.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Leigh Brown <leigh@solinno.co.uk>
Link: https://lkml.kernel.org/r/1409645719-20003-5-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/mvebu/armada-375.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/mvebu/armada-375.c b/drivers/clk/mvebu/armada-375.c index c991a4d95e10..c7af2242b796 100644 --- a/drivers/clk/mvebu/armada-375.c +++ b/drivers/clk/mvebu/armada-375.c @@ -27,14 +27,14 @@ * all modified at the same time, and not separately as for the Armada * 370 or the Armada XP SoCs. * - * SAR0[21:17] : CPU frequency DDR frequency L2 frequency + * SAR1[21:17] : CPU frequency DDR frequency L2 frequency * 6 = 400 MHz 400 MHz 200 MHz * 15 = 600 MHz 600 MHz 300 MHz * 21 = 800 MHz 534 MHz 400 MHz * 25 = 1000 MHz 500 MHz 500 MHz * others reserved. * - * SAR0[22] : TCLK frequency + * SAR1[22] : TCLK frequency * 0 = 166 MHz * 1 = 200 MHz */ |