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authorAngeloGioacchino Del Regno2022-01-03 15:37:12 +0100
committerStephen Boyd2022-01-06 18:27:10 -0800
commitd95abcab7b4aef11b29a5342b11fa60fd211929f (patch)
tree9d3d3704ced7bb418928a5a4ab6fdd240bdf9157 /drivers/clk
parent4233463866796affc6674888e4cbaa24e0ff7965 (diff)
clk: mediatek: clk-gate: Use regmap_{set/clear}_bits helpers
Appropriately change calls to regmap_update_bits() with regmap_set_bits() and regmap_clear_bits() for improved readability. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220103143712.46675-2-angelogioacchino.delregno@collabora.com Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/mediatek/clk-gate.c6
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
index 957fa1d68f07..5d88b428565b 100644
--- a/drivers/clk/mediatek/clk-gate.c
+++ b/drivers/clk/mediatek/clk-gate.c
@@ -53,17 +53,15 @@ static void mtk_cg_clr_bit(struct clk_hw *hw)
static void mtk_cg_set_bit_no_setclr(struct clk_hw *hw)
{
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
- u32 cgbit = BIT(cg->bit);
- regmap_update_bits(cg->regmap, cg->sta_ofs, cgbit, cgbit);
+ regmap_set_bits(cg->regmap, cg->sta_ofs, BIT(cg->bit));
}
static void mtk_cg_clr_bit_no_setclr(struct clk_hw *hw)
{
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
- u32 cgbit = BIT(cg->bit);
- regmap_update_bits(cg->regmap, cg->sta_ofs, cgbit, 0);
+ regmap_clear_bits(cg->regmap, cg->sta_ofs, BIT(cg->bit));
}
static int mtk_cg_enable(struct clk_hw *hw)