diff options
| author | Paul Cercueil | 2019-03-19 15:05:36 +0100 |
|---|---|---|
| committer | Stephen Boyd | 2019-04-11 13:41:11 -0700 |
| commit | eaa9558d35aee594c9658d92852e537a0fb897d7 (patch) | |
| tree | fa8c13bddb58ebfaea2be50daf2a5f5c51da4057 /drivers/clk | |
| parent | 93dc07f8b089ee073075c22873ab707225e192b5 (diff) | |
clk: ingenic: jz4725b: Add UDC PHY clock
Add clock for the USB Device Controller PHY.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/ingenic/jz4725b-cgu.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/ingenic/jz4725b-cgu.c b/drivers/clk/ingenic/jz4725b-cgu.c index 584ff4ff81c7..8901ea0295b7 100644 --- a/drivers/clk/ingenic/jz4725b-cgu.c +++ b/drivers/clk/ingenic/jz4725b-cgu.c @@ -205,6 +205,12 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { .parents = { JZ4725B_CLK_EXT512, JZ4725B_CLK_OSC32K, -1, -1 }, .mux = { CGU_REG_OPCR, 2, 1}, }, + + [JZ4725B_CLK_UDC_PHY] = { + "udc_phy", CGU_CLK_GATE, + .parents = { JZ4725B_CLK_EXT, -1, -1, -1 }, + .gate = { CGU_REG_OPCR, 6, true }, + }, }; static void __init jz4725b_cgu_init(struct device_node *np) |