diff options
| author | Minas Harutyunyan | 2020-05-21 10:05:44 +0400 |
|---|---|---|
| committer | Felipe Balbi | 2020-05-25 11:09:44 +0300 |
| commit | 65dc2e725286106f99c6f6b78e3d9c52c15f3a9c (patch) | |
| tree | 267a2f9b4db38c3354448e3ad17a5774896b188b /drivers/clocksource/timer-gx6605s.c | |
| parent | 4cda340a455b425f7df9657aaaa78a75757d940d (diff) | |
usb: dwc2: Update Core Reset programming flow.
Starting from core version 4.20a Core Reset flow is changed.
Introduced new bit in GRSTCTL register - GRSTCTL_CSFTRST_DONE.
Core Reset new programming flow steps are follow:
1. Set GRSTCTL_CSFTRST bit.
2. Wait for bit GRSTCTL_CSFTRST_DONE is set.
3. Clear GRSTCTL_CSFTRST and GRSTCTL_CSFTRST_DONE bits.
Check core version functionality separated from dwc2_get_hwparams() to
new dwc2_check_core_version() function because Core Reset flow depend
on SNPSID.
Signed-off-by: Minas Harutyunyan <hminas@synopsys.com>
Signed-off-by: Felipe Balbi <balbi@kernel.org>
Diffstat (limited to 'drivers/clocksource/timer-gx6605s.c')
0 files changed, 0 insertions, 0 deletions