diff options
| author | Jack Xu | 2020-11-06 19:28:00 +0800 |
|---|---|---|
| committer | Herbert Xu | 2020-11-13 20:38:52 +1100 |
| commit | 767358119fca655056eb7340eb8a0ec4652bc888 (patch) | |
| tree | 3012e5752548409782d059fc5d1a0008380bd3ea /drivers/crypto | |
| parent | cb439361a39bb8dcdd0856e9182e29678c8327af (diff) | |
crypto: qat - add clock enable CSR to chip info
Add global clock enable CSR to the chip info since the CSR offset
will be different in the next generation of QAT devices.
Signed-off-by: Jack Xu <jack.xu@intel.com>
Co-developed-by: Wojciech Ziemba <wojciech.ziemba@intel.com>
Signed-off-by: Wojciech Ziemba <wojciech.ziemba@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto')
| -rw-r--r-- | drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h | 1 | ||||
| -rw-r--r-- | drivers/crypto/qat/qat_common/qat_hal.c | 10 |
2 files changed, 7 insertions, 4 deletions
diff --git a/drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h b/drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h index 5e2c0ef6d26c..1d6ab3407dc9 100644 --- a/drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h +++ b/drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h @@ -29,6 +29,7 @@ struct icp_qat_fw_loader_chip_info { u32 lm_size; u32 icp_rst_csr; u32 icp_rst_mask; + u32 glb_clk_enable_csr; bool fw_auth; }; diff --git a/drivers/crypto/qat/qat_common/qat_hal.c b/drivers/crypto/qat/qat_common/qat_hal.c index 0d64e074fb44..6e6bca281ab7 100644 --- a/drivers/crypto/qat/qat_common/qat_hal.c +++ b/drivers/crypto/qat/qat_common/qat_hal.c @@ -471,11 +471,11 @@ static int qat_hal_init_esram(struct icp_qat_fw_loader_handle *handle) #define SHRAM_INIT_CYCLES 2060 int qat_hal_clr_reset(struct icp_qat_fw_loader_handle *handle) { + unsigned int clk_csr = handle->chip_info->glb_clk_enable_csr; unsigned int reset_mask = handle->chip_info->icp_rst_mask; unsigned int reset_csr = handle->chip_info->icp_rst_csr; unsigned long ae_mask = handle->hal_handle->ae_mask; unsigned char ae = 0; - unsigned int clk_csr; unsigned int times = 100; unsigned int csr_val; @@ -490,9 +490,9 @@ int qat_hal_clr_reset(struct icp_qat_fw_loader_handle *handle) csr_val &= reset_mask; } while (csr_val); /* enable clock */ - clk_csr = GET_CAP_CSR(handle, ICP_GLOBAL_CLK_ENABLE); - clk_csr |= reset_mask; - SET_CAP_CSR(handle, ICP_GLOBAL_CLK_ENABLE, clk_csr); + csr_val = GET_CAP_CSR(handle, clk_csr); + csr_val |= reset_mask; + SET_CAP_CSR(handle, clk_csr, csr_val); if (qat_hal_check_ae_alive(handle)) goto out_err; @@ -701,6 +701,7 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle, handle->chip_info->lm2lm3 = false; handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG; handle->chip_info->icp_rst_csr = ICP_RESET; + handle->chip_info->glb_clk_enable_csr = ICP_GLOBAL_CLK_ENABLE; handle->chip_info->fw_auth = true; break; case PCI_DEVICE_ID_INTEL_QAT_DH895XCC: @@ -709,6 +710,7 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle, handle->chip_info->lm2lm3 = false; handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG; handle->chip_info->icp_rst_csr = ICP_RESET; + handle->chip_info->glb_clk_enable_csr = ICP_GLOBAL_CLK_ENABLE; handle->chip_info->fw_auth = false; break; default: |