diff options
| author | Dan Williams | 2022-08-02 13:27:44 -0700 |
|---|---|---|
| committer | Dan Williams | 2022-08-05 08:41:02 -0700 |
| commit | 8d428542571428fb68b5c41b092ae70d2fc2cd17 (patch) | |
| tree | c68d5e6b422f5f3ce9bd7eabcecda7931605fa50 /drivers/cxl | |
| parent | 817b279467404ae3b16db8886b87eaefd8b13a6d (diff) | |
cxl/region: Fix port setup uninitialized variable warnings
0day robot reports:
drivers/cxl/core/region.c:1068 cxl_port_setup_targets() error: uninitialized symbol 'eiw'.
drivers/cxl/core/region.c:1068 cxl_port_setup_targets() error: uninitialized symbol 'peig'.
drivers/cxl/core/region.c:1068 cxl_port_setup_targets() error: uninitialized symbol 'peiw'.
...which are all valid reports. Add debug statement to consume the,
albeit unexpected, errors.
Fixes: 27b3f8d13830 ("cxl/region: Program target lists")
Reported-by: kernel test robot <lkp@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/165951147487.967013.929590444907251028.stgit@dwillia2-xfh.jf.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl')
| -rw-r--r-- | drivers/cxl/core/region.c | 25 |
1 files changed, 22 insertions, 3 deletions
diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 594e5bf9e5f8..25502c9c368c 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -987,11 +987,30 @@ static int cxl_port_setup_targets(struct cxl_port *port, parent_iw = parent_cxld->interleave_ways; } - granularity_to_cxl(parent_ig, &peig); - ways_to_cxl(parent_iw, &peiw); + rc = granularity_to_cxl(parent_ig, &peig); + if (rc) { + dev_dbg(&cxlr->dev, "%s:%s: invalid parent granularity: %d\n", + dev_name(parent_port->uport), + dev_name(&parent_port->dev), parent_ig); + return rc; + } + + rc = ways_to_cxl(parent_iw, &peiw); + if (rc) { + dev_dbg(&cxlr->dev, "%s:%s: invalid parent interleave: %d\n", + dev_name(parent_port->uport), + dev_name(&parent_port->dev), parent_iw); + return rc; + } iw = cxl_rr->nr_targets; - ways_to_cxl(iw, &eiw); + rc = ways_to_cxl(iw, &eiw); + if (rc) { + dev_dbg(&cxlr->dev, "%s:%s: invalid port interleave: %d\n", + dev_name(port->uport), dev_name(&port->dev), iw); + return rc; + } + if (cxl_rr->nr_targets > 1) { u32 address_bit = max(peig + peiw, eiw + peig); |