diff options
| author | Jie Yang | 2016-01-07 08:39:33 +0800 |
|---|---|---|
| committer | Vinod Koul | 2016-01-25 09:49:55 +0530 |
| commit | c9784a467380dfbd8070c735e651af07331172d9 (patch) | |
| tree | e531babe0b65e916b1df88698dae26e57ab77d95 /drivers/dma/dw | |
| parent | 92e963f50fc74041b5e9e744c330dca48e04f08d (diff) | |
dmaengine: dw: fix a typo for bitfields of CTL_LO
The offset of SINC should be 9, not 7, here fix this
typo.
Signed-off-by: Jie Yang <yang.jie@intel.com>
Acked-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'drivers/dma/dw')
| -rw-r--r-- | drivers/dma/dw/regs.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h index 241ff2b1402b..0a50c18d85b8 100644 --- a/drivers/dma/dw/regs.h +++ b/drivers/dma/dw/regs.h @@ -150,7 +150,7 @@ enum dw_dma_msize { #define DWC_CTLL_DST_INC (0<<7) /* DAR update/not */ #define DWC_CTLL_DST_DEC (1<<7) #define DWC_CTLL_DST_FIX (2<<7) -#define DWC_CTLL_SRC_INC (0<<7) /* SAR update/not */ +#define DWC_CTLL_SRC_INC (0<<9) /* SAR update/not */ #define DWC_CTLL_SRC_DEC (1<<9) #define DWC_CTLL_SRC_FIX (2<<9) #define DWC_CTLL_DST_MSIZE(n) ((n)<<11) /* burst, #elements */ |