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authorViresh KUMAR2011-03-04 15:42:51 +0530
committerVinod Koul2011-03-07 01:12:28 +0530
commitee66509d7f354eecb45ac99f21ea6aa8650dea7e (patch)
tree206438e7c0ef9a7f0633fe44d6f306fdbf4b0b4e /drivers/dma/dw_dmac_regs.h
parent59c22fc11d12b69da36c6585a38229863ba0bb16 (diff)
dw_dmac: Allow src/dst msize & flow controller to be configured at runtime
Msize or Burst Size is peripheral dependent in case of prep_slave_sg and cyclic_prep transfers, and in case of memcpy transfers it is platform dependent. So msize configuration must come from platform data. Also some peripherals (ex: JPEG), need to be flow controller for dma transfers, so this information in case of slave_sg & cyclic_prep transfers must come from platform data. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'drivers/dma/dw_dmac_regs.h')
-rw-r--r--drivers/dma/dw_dmac_regs.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/dma/dw_dmac_regs.h b/drivers/dma/dw_dmac_regs.h
index 6a8e6d35f359..9a32964bf795 100644
--- a/drivers/dma/dw_dmac_regs.h
+++ b/drivers/dma/dw_dmac_regs.h
@@ -86,6 +86,7 @@ struct dw_dma_regs {
#define DWC_CTLL_SRC_MSIZE(n) ((n)<<14)
#define DWC_CTLL_S_GATH_EN (1 << 17) /* src gather, !FIX */
#define DWC_CTLL_D_SCAT_EN (1 << 18) /* dst scatter, !FIX */
+#define DWC_CTLL_FC(n) ((n) << 20)
#define DWC_CTLL_FC_M2M (0 << 20) /* mem-to-mem */
#define DWC_CTLL_FC_M2P (1 << 20) /* mem-to-periph */
#define DWC_CTLL_FC_P2M (2 << 20) /* periph-to-mem */