diff options
| author | Peter Ujfalusi | 2020-07-17 15:09:02 +0300 |
|---|---|---|
| committer | Vinod Koul | 2020-07-27 14:23:03 +0530 |
| commit | 44385c4171d03b1aa030f3f21a6fce2f6edcfdab (patch) | |
| tree | f4953c566022f12e34028e4a19364e3526078a93 /drivers/dma/ti | |
| parent | 4b545ebfc371552cda7ce97a4beb485da9ef89cd (diff) | |
dmaengine: ti: k3-udma: Use defines for capabilities register parsing
Add defines for the CAP register fields to make the code self explaining.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Link: https://lore.kernel.org/r/20200717120903.8774-2-peter.ujfalusi@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/dma/ti')
| -rw-r--r-- | drivers/dma/ti/k3-udma.c | 12 | ||||
| -rw-r--r-- | drivers/dma/ti/k3-udma.h | 6 |
2 files changed, 12 insertions, 6 deletions
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 677541434ad1..e1b7cde793e3 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -3209,13 +3209,13 @@ static int udma_setup_resources(struct udma_dev *ud) "ti,sci-rm-range-rchan", "ti,sci-rm-range-rflow" }; - cap2 = udma_read(ud->mmrs[MMR_GCFG], 0x28); - cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c); + cap2 = udma_read(ud->mmrs[MMR_GCFG], UDMA_CAP_REG(2)); + cap3 = udma_read(ud->mmrs[MMR_GCFG], UDMA_CAP_REG(3)); - ud->rflow_cnt = cap3 & 0x3fff; - ud->tchan_cnt = cap2 & 0x1ff; - ud->echan_cnt = (cap2 >> 9) & 0x1ff; - ud->rchan_cnt = (cap2 >> 18) & 0x1ff; + ud->rflow_cnt = UDMA_CAP3_RFLOW_CNT(cap3); + ud->tchan_cnt = UDMA_CAP2_TCHAN_CNT(cap2); + ud->echan_cnt = UDMA_CAP2_ECHAN_CNT(cap2); + ud->rchan_cnt = UDMA_CAP2_RCHAN_CNT(cap2); ch_count = ud->tchan_cnt + ud->rchan_cnt; ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt), diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h index a8ea1138e1a5..9534f0ca29f4 100644 --- a/drivers/dma/ti/k3-udma.h +++ b/drivers/dma/ti/k3-udma.h @@ -37,6 +37,12 @@ #define UDMA_CHAN_RT_BCNT_REG 0x408 #define UDMA_CHAN_RT_SBCNT_REG 0x410 +/* UDMA_CAP Registers */ +#define UDMA_CAP2_TCHAN_CNT(val) ((val) & 0x1ff) +#define UDMA_CAP2_ECHAN_CNT(val) (((val) >> 9) & 0x1ff) +#define UDMA_CAP2_RCHAN_CNT(val) (((val) >> 18) & 0x1ff) +#define UDMA_CAP3_RFLOW_CNT(val) ((val) & 0x3fff) + /* UDMA_CHAN_RT_CTL_REG */ #define UDMA_CHAN_RT_CTL_EN BIT(31) #define UDMA_CHAN_RT_CTL_TDOWN BIT(30) |