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authorJosh Cartwright2012-11-13 17:26:48 -0600
committerMichal Simek2012-11-14 16:07:55 +0100
commit45aa2c27ada4829bc91bd80455bc67059ac06bc5 (patch)
tree988c0d412a6a59414b80eeb02813923032841476 /drivers/firmware
parente06f1a9ed7ebff170ba05d2606d079fb36c6a52d (diff)
clk: Add support for fundamental zynq clks
Provide simplified models for the necessary clocks on the zynq-7000 platform. Currently, the PLLs, the CPU clock network, and the basic peripheral clock networks (for SDIO, SMC, SPI, QSPI, UART) are modelled. OF bindings are also provided and documented. Signed-off-by: Josh Cartwright <josh.cartwright@ni.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'drivers/firmware')
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