diff options
| author | Mahesh Kumar | 2019-07-11 10:31:11 -0700 |
|---|---|---|
| committer | Lucas De Marchi | 2019-07-11 16:31:21 -0700 |
| commit | 3fd53262f0dd81361efcb5ccba8312525ee6c645 (patch) | |
| tree | 185cba553a2c29d76566ce47dec5545a15e42d37 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 30fcc338bc66f930dc7f692205474edb7ca6a607 (diff) | |
drm/i915/tgl: Add gmbus gpio pin to port mapping
Add default GPIO pin mapping for all ports. Tiger Lake has 3 combophy
ports and 6 TC ports, gpio pin1-3 are mapped to combophy & pin9-14 are
mapped to TC ports.
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190711173115.28296-18-lucas.demarchi@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ad96c5b4975c..62ac8a119602 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3254,8 +3254,10 @@ enum i915_power_well_id { #define GMBUS_PIN_10_TC2_ICP 10 #define GMBUS_PIN_11_TC3_ICP 11 #define GMBUS_PIN_12_TC4_ICP 12 +#define GMBUS_PIN_13_TC5_TGP 13 +#define GMBUS_PIN_14_TC6_TGP 14 -#define GMBUS_NUM_PINS 13 /* including 0 */ +#define GMBUS_NUM_PINS 15 /* including 0 */ #define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */ #define GMBUS_SW_CLR_INT (1 << 31) #define GMBUS_SW_RDY (1 << 30) |