diff options
| author | Michel Dänzer | 2009-06-16 17:29:06 +0200 |
|---|---|---|
| committer | Dave Airlie | 2009-06-19 09:28:20 +1000 |
| commit | 4e484e7dc5856ff5086b6329d82e36d4adaf1f02 (patch) | |
| tree | ca8d91c03f89732c36f44b30d01927802f4fa767 /drivers/gpu | |
| parent | 62369028c7e2039b821799b3db52f0d622f0e8b5 (diff) | |
radeon: Fix CP byte order on big endian architectures with KMS.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/radeon/r100.c | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_reg.h | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index 8f41f701f0b7..64a692c0c319 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c @@ -551,6 +551,9 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) /* cp setup */ WREG32(0x718, pre_write_timer | (pre_write_limit << 28)); WREG32(RADEON_CP_RB_CNTL, +#ifdef __BIG_ENDIAN + RADEON_BUF_SWAP_32BIT | +#endif REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | REG_SET(RADEON_RB_BLKSZ, rb_blksz) | REG_SET(RADEON_MAX_FETCH, max_fetch) | diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h index 6d3d90406a24..e1b618574461 100644 --- a/drivers/gpu/drm/radeon/radeon_reg.h +++ b/drivers/gpu/drm/radeon/radeon_reg.h @@ -3184,6 +3184,7 @@ # define RADEON_RB_BUFSZ_MASK (0x3f << 0) # define RADEON_RB_BLKSZ_SHIFT 8 # define RADEON_RB_BLKSZ_MASK (0x3f << 8) +# define RADEON_BUF_SWAP_32BIT (1 << 17) # define RADEON_MAX_FETCH_SHIFT 18 # define RADEON_MAX_FETCH_MASK (0x3 << 18) # define RADEON_RB_NO_UPDATE (1 << 27) |