diff options
| author | Ben Skeggs | 2012-08-19 15:53:15 +1000 |
|---|---|---|
| committer | Ben Skeggs | 2012-10-03 13:13:05 +1000 |
| commit | 9456f7d1beb8f7cfd99300e6028b3b2667c2ebd5 (patch) | |
| tree | 8a7a8429bcde2cfb9c454a2202ec47471255caa6 /drivers/gpu | |
| parent | 368be5f1b84b3356eb03ad2ccaf073e2fbb7fc4e (diff) | |
drm/nouveau: add defines for internal class names
Will probably flesh the documentation of the classes out a bit too at some
later point.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/include/core/class.h | 49 |
1 files changed, 35 insertions, 14 deletions
diff --git a/drivers/gpu/drm/nouveau/core/include/core/class.h b/drivers/gpu/drm/nouveau/core/include/core/class.h index b0e1948f4e71..6180ae9800fc 100644 --- a/drivers/gpu/drm/nouveau/core/include/core/class.h +++ b/drivers/gpu/drm/nouveau/core/include/core/class.h @@ -1,8 +1,11 @@ #ifndef __NOUVEAU_CLASS_H__ #define __NOUVEAU_CLASS_H__ -/* 0080: NV_DEVICE +/* Device class + * + * 0080: NV_DEVICE */ +#define NV_DEVICE_CLASS 0x00000080 #define NV_DEVICE_DISABLE_IDENTIFY 0x0000000000000001ULL #define NV_DEVICE_DISABLE_MMIO 0x0000000000000002ULL @@ -27,10 +30,15 @@ struct nv_device_class { u64 debug0; /* as above, but *internal* ids, and *NOT* ABI */ }; -/* 0002: NV_DMA_FROM_MEMORY +/* DMA object classes + * + * 0002: NV_DMA_FROM_MEMORY * 0003: NV_DMA_TO_MEMORY * 003d: NV_DMA_IN_MEMORY */ +#define NV_DMA_FROM_MEMORY_CLASS 0x00000002 +#define NV_DMA_TO_MEMORY_CLASS 0x00000003 +#define NV_DMA_IN_MEMORY_CLASS 0x0000003d #define NV_DMA_TARGET_MASK 0x000000ff #define NV_DMA_TARGET_VM 0x00000000 @@ -51,13 +59,21 @@ struct nv_dma_class { u64 limit; }; -/* 006b: NV03_CHANNEL_DMA +/* DMA FIFO channel classes + * + * 006b: NV03_CHANNEL_DMA * 006e: NV10_CHANNEL_DMA * 176e: NV17_CHANNEL_DMA * 406e: NV40_CHANNEL_DMA * 506e: NV50_CHANNEL_DMA * 826e: NV84_CHANNEL_DMA */ +#define NV03_CHANNEL_DMA_CLASS 0x0000006b +#define NV10_CHANNEL_DMA_CLASS 0x0000006e +#define NV17_CHANNEL_DMA_CLASS 0x0000176e +#define NV40_CHANNEL_DMA_CLASS 0x0000406e +#define NV50_CHANNEL_DMA_CLASS 0x0000506e +#define NV84_CHANNEL_DMA_CLASS 0x0000826e struct nv03_channel_dma_class { u32 pushbuf; @@ -65,27 +81,32 @@ struct nv03_channel_dma_class { u64 offset; }; -/* 506f: NV50_CHANNEL_IND +/* Indirect FIFO channel classes + * + * 506f: NV50_CHANNEL_IND * 826f: NV84_CHANNEL_IND * 906f: NVC0_CHANNEL_IND + * a06f: NVE0_CHANNEL_IND */ +#define NV50_CHANNEL_IND_CLASS 0x0000506f +#define NV84_CHANNEL_IND_CLASS 0x0000826f +#define NVC0_CHANNEL_IND_CLASS 0x0000906f +#define NVE0_CHANNEL_IND_CLASS 0x0000a06f + struct nv50_channel_ind_class { u32 pushbuf; u32 ilength; u64 ioffset; }; -/* a06f: NVE0_CHANNEL_IND - */ - -#define NVE0_CHANNEL_IND_ENGINE_GR 0x00000001 -#define NVE0_CHANNEL_IND_ENGINE_VP 0x00000002 -#define NVE0_CHANNEL_IND_ENGINE_PPP 0x00000004 -#define NVE0_CHANNEL_IND_ENGINE_BSP 0x00000008 -#define NVE0_CHANNEL_IND_ENGINE_CE0 0x00000010 -#define NVE0_CHANNEL_IND_ENGINE_CE1 0x00000020 -#define NVE0_CHANNEL_IND_ENGINE_ENC 0x00000040 +#define NVE0_CHANNEL_IND_ENGINE_GR 0x00000001 +#define NVE0_CHANNEL_IND_ENGINE_VP 0x00000002 +#define NVE0_CHANNEL_IND_ENGINE_PPP 0x00000004 +#define NVE0_CHANNEL_IND_ENGINE_BSP 0x00000008 +#define NVE0_CHANNEL_IND_ENGINE_CE0 0x00000010 +#define NVE0_CHANNEL_IND_ENGINE_CE1 0x00000020 +#define NVE0_CHANNEL_IND_ENGINE_ENC 0x00000040 struct nve0_channel_ind_class { u32 pushbuf; |